Haojie Ye 叶皓桀

Deep Learning Performance Architect · NVIDIA

I build performance models that explain how AI workloads use GPU hardware. At NVIDIA, I use those insights to evaluate architecture tradeoffs and guide engineering and product decisions.

My work spans LLM prefill and decode, video generation, and agent-assisted performance analysis. I connect attention, precision, and parallelism choices to system performance, taking studies from model assumptions and simulation through validation and technical recommendations.

I earned my Ph.D. in Computer Science and Engineering at the University of Michigan, advised by Prof. Trevor Mudge. My research connects algorithms and systems through hardware-software co-design, with publications at HPCA, ASPLOS, MICRO, ISCA, VLDB, and PACT.

Resume PDF yehaojie@umich.edu GitHub

Selected Highlights

2026 Industry Led LLM and video-generation performance studies; developed an agent-assisted tool to explain performance differences.
2025 HPCA First-author paper Palermo on protocol-hardware co-design for oblivious memory.
2024/10 NVIDIA Joined NVIDIA as a Deep Learning Performance Architect in Santa Clara.
2024/09 Ph.D. Completed my Ph.D. at the University of Michigan.

Industry Experience

My experience includes performance modeling for the NVIDIA RTX PRO 6000 Blackwell family and Rubin architecture studies. I focus on how model structure and execution strategy interact with compute, memory, and communication limits.

NVIDIA — Deep Learning Performance Architect

Performance Modeling and Architecture Pathfinding · Santa Clara, CA

Oct 2024 – Present
  • Generative AI performance: Led studies of LLM prefill and decode and video generation, analyzing attention and precision choices to identify GPU bottlenecks and evaluate product tradeoffs.
  • Parallelism and model validation: Modeled tensor, context, and expert parallelism and implemented simulation capabilities for sparse attention. Validated model shapes, execution mappings, and run assumptions to make performance comparisons more reliable.
  • Agent-assisted analysis: Independently developed a component that reconciles execution mappings, explains differences between projections, and identifies outliers. Integrated it into a broader workflow for repeatable comparison and targeted debugging.
  • Architecture guidance: Evaluated compute, memory, and interconnect tradeoffs for GPU architecture studies. Controlled for execution-mapping differences when interpreting end-to-end results and forming engineering and product recommendations.
  • Technical leadership: Presented findings across teams and developed materials to teach colleagues how to run, validate, and explain performance studies.
LLM InferenceVideo Generation GPU ArchitecturePerformance Modeling AI AgentsMemory Systems Tensor / Expert ParallelismHardware-Software Co-Design

NVIDIA — Deep Learning Performance Architect Intern

Santa Clara, CA

May 2023 – Aug 2023
  • Researched performance modeling of large language models on future GPU architectures.

Micron Technology — Advanced Hardware Development Intern

Allen, TX

May 2022 – Aug 2022
  • Researched enhanced in-memory computing functions and memory-system design.

Selected Research

My academic work pairs workload characterization with architecture and system design to improve the efficiency of data-intensive computation. Selected papers below cover recommendation inference, GPU and memory systems, graph processing, and LLM fine-tuning. See Google Scholar for the full publication list.

HPCA'25 Protocol-Hardware Co-Design · Oblivious Memory

Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design

H. Ye, Y. Xia, Y. Chen, K.-Y. Chen, Y. Yuan, S. Deng, B. Kasikci, T. Mudge, N. Talati
HPCA 2025First author

Palermo co-designs an oblivious RAM protocol and hardware controller to overlap memory operations while preserving correctness and security guarantees. The paper evaluates how protocol and architecture choices reduce the performance cost of protecting memory access patterns.

ASPLOS'23 Recommendation Inference · Embedding Reuse

GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference

H. Ye, S. Vedula, Y. Chen, Y. Yang, A. Bronstein, R. Dreslinski, T. Mudge, N. Talati
ASPLOS 2023First author

GRACE clusters an item co-occurrence graph and caches embedding partial sums to reduce recommendation inference memory traffic. It pairs an algorithmic approach to recurring item combinations with a scalable system design.

IISWC'24 LLM Fine-Tuning · Throughput and Cost Modeling

Understanding the Performance and Estimating the Cost of LLM Fine-Tuning

Y. Xia, J. Kim, Y. Chen, H. Ye, S. Kundu, C. Hao, N. Talati

This work characterizes single-GPU fine-tuning of sparse and dense mixture-of-experts language models. An analytical model estimates throughput and cloud training cost to support infrastructure choices.

VLDB'24 GPU Systems · Temporal Motif Mining

Everest: GPU-Accelerated System For Mining Temporal Motifs

Y. Yuan, H. Ye, S. Vedula, W. Kaza, N. Talati

Everest accelerates temporal motif mining on GPUs through query-specific code generation, runtime load balancing, and multi-GPU graph partitioning. It connects graph-query structure to efficient parallel execution.

PACT'22 Multi-GPU · Remote Memory · Locality

Locality-aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems

L. Belayneh, H. Ye, K.-Y. Chen, D. Blaauw, T. Mudge, R. Dreslinski, N. Talati

This work introduces locality-adaptive remote memory transfers and a remote-only cache for multi-GPU systems. The architecture targets remote access latency by matching transfer and caching behavior to workload locality.

ISCA'22 Graph Pattern Mining · Near-Data Processing

NDMiner: Accelerating Graph Pattern Mining Using Near Data Processing

N. Talati, H. Ye, Y. Yang, L. Belayneh, K.-Y. Chen, D. Blaauw, T. Mudge, R. Dreslinski

NDMiner combines near-data execution, compiler support, and memory mapping to accelerate graph pattern mining. The design addresses the irregular memory access and control flow that make this workload difficult to execute efficiently.

MICRO'22 Temporal Motif Mining · Accelerator Design

Mint: An Accelerator For Mining Temporal Motifs

N. Talati, H. Ye, S. Vedula, K.-Y. Chen, Y. Chen, D. Liu, Y. Yuan, D. Blaauw, A. Bronstein, T. Mudge, R. Dreslinski

Mint introduces an accelerator architecture and programming model for temporal motif mining. It exploits parallelism while handling both structural and temporal constraints in graph queries.

ICS'20 Sparse Matrix-Vector Multiplication · Systolic Arrays

Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices

X. He, S. Pal, A. Amarnath, S. Feng, D.-H. Park, A. Rovinski, H. Ye, Y. Chen, R. Dreslinski, T. Mudge

Sparse-TPU co-designs sparse matrix packing and a systolic-array architecture to improve sparse matrix-vector multiplication efficiency. The work examines how data representation and hardware support can make better use of array resources.

Education

Ph.D., Computer Science & Engineering

University of Michigan, Ann Arbor · Advised by Prof. Trevor Mudge

GPA 4.0/4.0 · Focus: Computer Architecture for AI workloads

2021 – 2024

M.S.E., Computer Science & Engineering

University of Michigan, Ann Arbor

GPA 4.0/4.0

2019 – 2021

B.S.E., Computer Engineering

University of Michigan, Ann Arbor

2017 – 2019

B.S.E., Electrical & Computer Engineering

Shanghai Jiao Tong University

2015 – 2019

Beyond Work

  • Piano player and electronic music producer — Vaporwave & ambient experiments
  • Experimental film enthusiast — Tarkovsky, Lynch, early Kubrick
  • Philosophy of mind and consciousness — from Descartes to Chalmers